Algorithmic aspects of VLSI layout / edited by Majid Sarrafzadeh, D.T. Lee



Digitised Book 216.73.216.10 (0)
Algorithmic aspects of VLSI layout / edited by Majid Sarrafzadeh, D.T. Lee

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Information About

In the past two decades, research in VLSI physical design has been directed towards automation of layout process. Circuit layout techniques are developed with an aim to produce layouts with a small area. In this book there are 14 articles dealing with various stages of the VLSI layout problem written by leading experts in the field. Topics include partitioning, floorplanning. placement, global routing, detailed routing and layout verification. Some chapters are review articles, giving the state of-the art of the problems related to timing driven placement, global and detailed routing, and circuit partitioning Others are research articles, giving recent findings of or new approaches to the above mentioned problems. It will serve as a good reference for both researchers and professionals who work in this field.

Subjects

Integrated circuits--Very large scale integration--Design and construction--Data processing Computer-aided design Algorithms

Categories

Science and technology

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Additional Details

Title
Algorithmic aspects of VLSI layout / edited by Majid Sarrafzadeh, D.T. Lee
Subject
  • Integrated circuits--Very large scale integration--Design and construction--Data processing
  • Computer-aided design
  • Algorithms
Publisher
  • World Scientific,
  • National Library Board Singapore,
Contributors
  • Sarrafzadeh, Majid
  • Lee, D. T.
Digital Description
application/pdf, x, 397 p. ill.
Table of Contents
  • Issues in timing driven layout -- Binary formulations for placement and routing problems -- A survey of parallel algorithms for VLSI cell placement -- Approximate solutions for graph and hypergraph partitioning -- Integer program formulations of global routing and placement problems -- Circuit partitioning algorithms based on geometry model -- The three-dimensional channel routing problem -- On the Manhattan and knock-knee routing models -- Switch-box routing under the two-overlap wiring model -- A note on the complexity of Stockmeyer's floorplan optimization technique -- An algorithm to eliminate all complex triangles in a maximal planar graph for use in VLSI floorplan -- Constrained via minimization and signed hypergraph partitioning -- The virtual dimensions of a straight line embedding of a plane graph -- Routing around two rectangles to minimize the layout area..
Copyright
  • All Rights Reserved. National Library Board Singapore 2009.